Low-frequency power amplifier

ABSTRACT

In a low-frequency power amplifier designed for Class B or AB operation which comprises a first complementary pair of transistors connected in the form of Darlington connection, and a second complementary pair of transistors connected in the form of Darlington connection, there is provided means for permitting a bias current to flow through said transistors, whether or not there is an input signal, thereby preventing notching distortion.

United States Patent Sekiya May 13, 1975 1 LOW-FREQUENCY POWER AMPLIFIER[56] References Cited [75] Inventor: Mamoru Sekiya, Nagoya, Japan NITEDTATES PATENTS 3,550,025 12/1970 Stodolskyl .v 330/17 [73] Assignee.ShIn-ShIraSuna Electric Corporation, g y AiChLken, 3,611,170 10/1971Wheatley 330/17 X J 1 apdn Primary ExaminerJames B. Mullins [22] Filed:Feb. 11,1974 211 Appl. No: 441,420 ABSTRACT In a low-frequency poweramplifier designed for Class [30] Foreign Application Priority Data B orAB operation Vi/hICh comprises a first complementary pair of transistorsconnected in the form of July 19, 1973 Japan 48-82268 DarlingtonConnection and a Second complementary pair of transistors connected inthe form of Darlington [52] US. Cl. 330/13, 330/17, 3333062224connection, there is provided means for permitting a I Cl H03f biascurrent to flow through said transistors, whether [51] nt. or not therean input Signal thereby preventing [58] Field of Search 330/13, l5, 17,18,22, notching distortion 1 Claim, 2 Drawing Figures 1 LOW-FREQUENCYPOWER AMPLIFIER This invention relates to improvements in lowfrequencypower amplifier circuits.

Most of the low-frequency power transistor amplifiers which haveextensively been used heretofore, are single-ended push-pull (referredto as SEPP hereinafter) circuits, especially complementary SEPP circuitsusing complementary pairs of transistors connected in the form ofDarlington connection. Such circuits are commonly designed for class Bor AB push-pull operation which is advantageous in respect of powersource capacity, collector loss, type of heat dissipating means, etc.With such circuit arrangements, however, there inevitably occurcrossover distortion, notching distortion and so forth. Crossoverdistortion can be prevented by flowing a high bias current through eachtransistor, whereas notching distortion cannot be avoided unless anarrangement for class A operation is adopted, since such distortion isone which results from switching of the transistors. Obviously, class Aoperation is disadvantageous in that it is accompanied by much greaterpower loss.

Accordingly, it is a primary object of this invention to provide alow-frequency power amplifier circuit arrangement which is designed forclass B or AB operation and yet free from not only crossover distortionbut also notching distortion.

According to an aspect of this invention, there is provided alow-frequency power amplifier circuit arrangement designed for Class Bor AB operation, comprising a first transistor of a first conductivitytype, a second transistor of a second conductivity type having the basethereof connected with the collector of said first transistor, a firstdiode having the positive and negative electrodes thereof connected tothe emitter of said first transistor and the collector of said secondtransistor respectively, a third transistor of said second conductivitytype, a fourth transistor of said first conductivity type having thebase thereof connected with the collector of said third transistor, asecond diode having the negative and positive electrodes thereofconnected to the emitter of said third transistor and the collector ofsaid fourth transistor respectively, a resistor connected between theemitters of said first and third transistors, and a bias circuit meansconnected between the bases of said first and third transistors, thecollectors of said second and fourth transistors being connected to aload.

Other objects, features and advantages of this invention will becomeapparent from the following description taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a schematic circuit diagram showing the low-frequency poweramplifier according to an embodiment of this invention; and

FIG. 2 is a view useful for explaining the operation of the amplifiershown in FIG. 1.

Referring to FIG. 1, a differential amplifier 4 is provided whichcomprises a pair of PNP transistors T and T the emitters of which arecoupled to each other and to a power source terminal 1 through aresistor 5. The collector of the transistor T is coupled direct toanother power source terminal 2 to which is also coupled the collectorof the transistor T through a resistor 6. To the base of the transistorT are connected a capacitor 7 the other end of which constitutes aninput tenninal 8, and a resistor 9 which is grounded at the other end.The base of the transistor T is connected to a load R through a resistor10 and also grounded through a series circuit of a capacitor 11 andresistor 12.

An NPN transistor T serves as a power driver with the base thereofcoupled to the collector of the transistor T and with the emitterthereof coupled to the power source terminal 2.

An NPN transistor Q, has its base connected to the collector of thepower driver transistor T through a bias circuit 3 and also to the powersource terminal 1 through a constant current source 13. A PNP transistorQ has its base connected to the collector of the NPN transistor O, whichis coupled to the power source terminal 1 through a resistor R Theemitter of the PNP transistor O is coupled to the power source terminal1, and the collector thereof is coupled to the load R through a resistorR A diode D is provided which has its positive and negative electrodesconnected to the emitter of the NPN transistor Q, and the collector ofthe PNP transistor Q respectively.

A PNP transistor Q has its base connected direct to the collector of thepower driver transistor T and an NPN transistor Q, has its baseconnected direct to the collector of the PNP transistor 0;, which isalso coupled to the power source terminal 2 through a resistor R Theemitter of the NPN transistor 0 is connected to the power sourceterminal 2, and the collector thereof is coupled to the load R through aresistor R A sec ond diode D is provided which has its positive andnegative electrodes connected to the collector of the NPN transistor 0,and the emitter of the PNP transistor 0, respectively.

Between the emitters of the transistors Q and Q;, is connected aresistor R the function of which will be fully described later.

Description will now be made of the operation of the circuit shown inFIG. 1. When no signal is being applied to the input terminal 8, it isassumed that the voltages between the bases and the emitters of thetransistors Q and Q and V and V BB3 respectively, that the forwardvoltage drops across the diodes D, and D are V and V respectively, thatthe voltages across the resistor R is V and that the voltage across thebias circuit 3 is V,,, as shown in FIG. 2. In this case, the values ofthe resistors R, and R are so small and the current flowing through thetransistors Q and Q, are so low that the voltage drops across theseresistors can be neglected. Thus, it will readily be understood that thefollowing equation holds:

When an input signal is applied to the input terminal 8, and during eachpositive half cycle thereof, it is assumed that a current I is caused toflow through the load L as shown in FIG. 2. It is further assumed thatthe load current I is much greater than the bias current, and that thevoltage variations at the operating points of the transistors Q, and Qare a and B respectively. Then, the foregoing equation can be rewrittenas follows:

b HEl ans B) ern ass B) V (a ,8) [Usually, V (a 5)] Normally, thevoltage drop across the resistor R, due to the increase in the collectorcurrent is greater than the variations in the base-emitter voltage.Hence, the following relationships hold true:

In this case, the diode D is rendered conductive by the fact that theemitter-current of the transistor Q flows therethrough, whereas thediode D is rendered nonconductive by the fact that the voltagethereacross does not reach the level of the forward bias voltagethereof. Furthermore, the variation in the voltage across the resistor Ris small, and the current flowing therethrough is caused to flow throughthe transistor Q as emitter current, so that the variation in the latteris also small. In this way, since thevariation in the emitter current ofthe transistor O is small, the variation in the voltage drop across theresistor R is also small, so that the transistor Q is still conducting.Thus, during each positive half cycle of the input signal, both thetransistors Q and Q are conducting so that the signal is subject to nonotching distortion. During each negative half cycle of the inputsignal, the diode D is rendered nonconductive, so that the transistors Qand Q are kept conductive by being supplied with the bias current, aswill be readily apparent to those skilled in the art from what has beendescribed above.

In order to keep the transistors Q and Q supplied with the bias current,the values for the resistors R and R for shunting the collector currentsof the transistors Q and 0;, respectively, should preferably be selectedto be sufficiently greater than the input impedances between the basesand the emitters of the transistors Q and 0, so as to achieveconstant-current driving.

As will be understood from the foregoing, according to this invention,the bias current flowing through the first transistor Q will always bepermitted to flow into the emitter of the transistor Q via the resistorR whether or not there is an input signal; The current increased by theinput signal will be passed to the load through one of the diodes, andthe voltage across the resistor R will be prevented from changing by theother diode, so that the first and third transistors Q and Q will alwaysbe conducting. Thus, even when the operating point is set up to giveClass B or similar operation, notching distortion can be avoided whichresults from switching of transistors. The same effect can be producedeven when the resistors R and R are eliminated. Such resistors may beprovided between the emitters of the second and fourth transistors Q andQ and the power source. In order to make the operation more effective,the bias circuit 3 should preferably be onewhich provides a constantvoltage irrespective of input signals.

While the present invention has been described with respect to specificembodiments thereof, it should be understood that the invention is notrestricted to those embodiments but various modifications may be madetherein without departing from the spirit and scope of the invention asdefined in the appended claims.

What is claimed is:

l. A low-frequency amplifier circuit arrangement designed for ClassB orAB operation, comprising:

a first amplifier stage including a first transistor of a firstconductivity-type and a second transistor of a second conductivity-typehaving the base thereof connected with the collector of said firsttransistor; a second amplifier stage including a third transistor ofsaid second conductivity-type and a fourth transistor of said firstconductivity-type having the base thereof connected with the collectorof said third transistor; said second and fourth transistors having thecollectors thereof connected to a load to alternately drive said load;and means for preventing said first and third transistors from beingbrought into cut-off condition, regardless of whether one of said secondand fourth transistors are driving said load; said means comprising biascircuit means connected between the bases of said first and thirdtransistors, a non-grounded resistor through which the emitters of saidfirst and third transistors are connected to each other, a first diodehaving the anode and cathode thereof connected to the emitter of saidfirst transistor and the collector of said second transistorrespectively, and a second diode having the anode and cathode thereofconnected to the collector of said fourth transistor and the emitter ofsaid third transistor respectively.

1. A low-frequency amplifier circuit arrangement designed for Class ''''B'''' or ''''AB'''' operation, comprising: a first amplifier stage including a first transistor of a first conductivity-type and a second transistor of a seCond conductivity-type having the base thereof connected with the collector of said first transistor; a second amplifier stage including a third transistor of said second conductivity-type and a fourth transistor of said first conductivity-type having the base thereof connected with the collector of said third transistor; said second and fourth transistors having the collectors thereof connected to a load to alternately drive said load; and means for preventing said first and third transistors from being brought into cut-off condition, regardless of whether one of said second and fourth transistors are driving said load; said means comprising bias circuit means connected between the bases of said first and third transistors, a non-grounded resistor through which the emitters of said first and third transistors are connected to each other, a first diode having the anode and cathode thereof connected to the emitter of said first transistor and the collector of said second transistor respectively, and a second diode having the anode and cathode thereof connected to the collector of said fourth transistor and the emitter of said third transistor respectively. 